![]() (8)Bombardment with Arsenic atoms which penetrate in the wafer through the SiO2 thinner layer being retained by the SiO2 thicker layer. (7)Removal of the exposed photosensitive material. (6)Photolithographic exposition of this layer to UV light through a mask that defines the nMos transistors’s sources and drains. (5)Deposition of a photosensitive and etching resistant layer. The now defined transistors’s gates get insulated too. (4)Removal of a thin part of the SiO2 layer and immediate deposition of a new SiO2 layer, in order that the SiO2 layer surface stays renewed and totally cleaned. (3)Removal of the unexposed photosensitive material by a chemical own process. This way the nMOS and pMOS transistors’s Gates are created in n-doped Polysilicon. (2)Removal by etching of the Polysilicon layer below it. (6)Photolithographic exposition of this layer to UV light through a mask that defines the transistors’s gates.įrame 11 – (1)Removal of the exposed photosensitive material. (4)Deposition of an n-doped Polysilicon layer. (3)Removal of a thin part of the SiO2 layer and immediate deposition of a new SiO2 layer, in order that the SiO2 layer surface stays renewed and totally cleaned. (2)Removal by etching of Si3N4 and Polysilicon layers below it. (3)Deposition of an SiO2 much thicker layer over the SiO2 exposed layer.įrame 10 – (1)Removal of the unexposed photosensitive material by a chemical own process. (2)Removal by etching of the Si3N4 and Polysilicon layers in the areas not protected by the etching resistant material. (5)Photolithographic exposition of the wafer to UV light through a mask that will reveal the zones out of the transistors.įrame 9 – (1)Removal of the photosensitive material exposed. (4)Deposition of a photosensitive and etching resistant layer over the above ones. (3)Deposition of a Polysilicon layer followed by a Si3N4 layer. (2)Deposition of a renewed thin SiO2 layer. Due to its diffusion the Boron atoms are added to the wafer’s crystal structure, thus creating the p-doped well.įrame 8 – (1)Total removal of SiO2 layers by etching. The Boron atoms containing holes in its crystal structure (lack of electrons) provide the creation of a P (Positive) layer after its incorporation into the silicon crystal structure.įrame 7 -The ionization process is followed by an annealing process at high temperatures in order to reconstruct the crystal structures and incorporate the implanted atoms in it. (3) Bombardment and implantation of Boron atoms, which penetrate through the thin layer of SiO2 being retained in the thicker layer of SiO2. ![]() The protection granted by Si3N4 allows only the Polysilicon tops to be affected by this deposition, thereby protecting the parts of the wafer not to be affected.įrame 6 – (1)Removal of the unexposed photosensitive material by a chemical own process. (2)Deposition of another SiO2 much thicker layer over the SiO2 exposed layer. Due to its diffusion the Phosphorus atoms are added to the wafer’s crystal structure, thus creating the n-doped well. The Phosphorus atoms containing electrons in excess (more electrons than protons) provide the creation of a N (Negative) layer after its incorporation into the silicon crystal structure.įrame 5 – (1)The ionization process is followed by an annealing process at high temperatures in order to reconstruct the crystal structures and incorporate the implanted atoms in it. ![]() (2)Bombardment and implantation of Phosphorus atoms, which penetrate through the thin layer of SiO2 being retained by Si3N4 in the areas where it was not removed. (4)Removal of the exposed photosensitive material.įrame 4 – (1)Removal by etching of Si3N4 and Polysilicon layers in the areas not protected by the photosensitive layer. (3)By a photolithography process the wafer is exposed to UV light through previously developed masks that define the location of the n-doped wells where the pMOS will be created. (2)Deposition of a photosensitive and resistant to etching product layer over the above ones. Silicon Dioxide (SiO2) is used as a protective layer to the ultra clean silicon wafer’s surface and also as an insulating layer.įrame 3 – (1)Deposition of Polysilicon layer followed by a Silicon Nitride (Si3N4) layer. The number of frames is much smaller because we decided to accumulate many manufacturing phases in each frame, essentially standing out the way of manufacturing one transistor comprising two opposite, nMOS and pMOS.įrame 1 – The wafers taken from the silicon ingot are polished and cleaned of any impurities.įrame 2 – The wafer’s surface is oxidized. Let’s go through it step by step with the help of the tables in Figure 1-20. The manufacture of these transistors is very similar to what we saw for the nMOS transistors. ![]()
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